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-
- /* @(#)interreg.h 1.3 88/02/08 SMI */
-
- /*
- * Copyright (c) 1986 by Sun Microsystems, Inc.
- */
-
- /*
- * The interrupt register provides for the generation of software
- * interrupts and controls the video and clock hardware interrupts.
- */
- #define OBIO_INTERREG 0xA0000 /* address of interreg in obio space */
-
- #ifdef LOCORE
- #define INTERREG 0x0FFE6000 /* virtual address we map interreg to be at */
- #else
- #define INTERREG ((u_char *)(0x0FFE6000))
- #endif
-
- /*
- * Bits of the interrupt register.
- */
- #define IR_ENA_CLK7 0x80 /* r/w - enable clock level 7 interrupt */
- #define IR_ENA_CLK5 0x20 /* r/w - enable clock level 5 interrupt */
- #define IR_ENA_VID4 0x10 /* r/w - enable video level 4 interrupt */
- #define IR_SOFT_INT3 0x08 /* r/w - cause software level 3 interrupt */
- #define IR_SOFT_INT2 0x04 /* r/w - cause software level 2 interrupt */
- #define IR_SOFT_INT1 0x02 /* r/w - cause software level 1 interrupt */
- #define IR_ENA_INT 0x01 /* r/w - enable (all) interrupts */
-